Mentor Graphics to Highlight Altera Nios Soft Core Embedded Processor at IC Design Technical Forum

San Jose, Calif., April 15, 2002 -- Altera Corporation (Nasdaq: ALTR) today announced that Michael Bohm, chief scientist of the HDL Design division of Mentor Graphics Corporation (Nasdaq: MENT), will discuss design techniques for synthesizing high-density programmable logic devices (PLDs) embedded with Altera’s Nios^® soft core processor at the IC Design Technical Forum, April 15-16, 2002, in San Jose, Calif.

Bohm’s seminar session, "Designing High-Speed PLDs Using Embedded Processors," will provide designers with information and techniques needed to build system-on-a-programmable-chip (SOPC) solutions using Altera’s PLDs and the Nios soft core embedded processor. Bohm will also discuss Altera’s recently announced SOPC Builder tool, an automated system development tool that accelerates the process of integrating complex designs in Altera’s high-density PLDs. Bohm will deliver the presentation on Tuesday, April 16 at 11 a.m. PDT.

"With several Mentor Graphics customers using Altera’s high-density PLDs embedded with a Nios soft core processor, it is essential for us to arm them with the necessary tools and techniques to successfully synthesize their designs," said Bohm.

About Mentor Graphics’ IC Design Technical Forum

The 2nd Annual IC Design Technical Forum, hosted by the Silicon Valley Mentor Graphics Users Group, is a premier conference providing a focused forum for Mentor Graphics users to present and discuss their use of the Mentor software, new developments, future trends, innovative ideas and recent advancements exclusively on IC, ASIC and FPGA designs. More information about the IC Design Technical Forum is available at: http://www.mentorug.org/lugs/svlug/conferences/2002/.

About the Nios Soft Core Embedded Processor

Altera’s Nios soft core embedded processor is optimized for programmable logic and SOPC integration. One of Altera’s Excalibur embedded processor solutions, the Nios core is a general-purpose RISC processor that can be combined with user logic and programmed into an Altera PLD. The processor features a 16-bit instruction set and user-selectable 16- or 32-bit data paths, configurable for a wide range of applications. The Nios embedded processor is license and royalty free when used in Altera PLDs and HardCopy^™ devices.

About Altera

Altera Corporation (Nasdaq: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.

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