Menta exhibits at Chiplet Summit and presents its new scalable chiplet platform, MOSAICS-LP
Sophia Antipolis, January 23rd, 2024 – Menta, a deeptech company specializing in semiconductor design will attend Chiplet Summit to present MOSAICS-LP – an industrial platform specifically designed for the development of heterogeneous chips, using a universal chassis and a catalog of third-party chiplets. This platform is supported by the French government and the CEA-List, a research center specializing in intelligent digital systems.
The Second Annual Chiplet Summit is a pivotal gathering for chip designers and market players, providing insights into optimizing chiplet performance in speed, scalability, power efficiency, and flexibility. The summit facilitates networking, expert interactions, and exposure to a wide array of products and services, enabling participants to stay abreast of the latest advancements in chiplet technology.
Menta, is a pioneer in programmable logic solutions and will share a booth with its partner CEA-List.
In the current semiconductor manufacturing environment, conventional monolithic solutions give rise to issues related to energy consumption, scalability, and cost. MOSAICS-LP aims to tackle these challenges, in the booming environment of heightened production demands. MOSAICS-LP addresses the Edge Computing market, including Artificial Intelligence, IoT, robotic, automotive industry and 5G/6G markets; by offering competitive, scalable, high-performance, and energy-efficient solutions.
Vincent Markus, CEO of Menta declares “At the forefront of innovation, Menta, alongside our strategic research partner CEA-List, is proud to participate in the Second Annual Chiplet Summit, a crucial event for chip designers and market players in the United States. MOSAICS-LP redefines semiconductor solutions, addressing issues of energy and cost in traditional monolithic approaches. Our groundbreaking platform, centered on Edge Computing and embedded AI, features a unique architecture with a universal chassis and chiplets. Key advantages include scalability, energy efficiency, reduced development costs, and risk mitigation through pre-tested components, making MOSAICS-LP an innovative solution for the evolving semiconductor landscape.”
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- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
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