Panel ponders many-core ICs tripping 'the singularity'
Peter Clarke, EETimes
3/28/2012 12:09 PM EDT
That was the question put to a panel of some of the best minds in multicore processor theory and design assembled on Tuesday (March 27) by analyst Jon Peddie at the Multicore DevCon, part of DESIGN West being held here this week. A small but enthusiastic audience was there to listen.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- Tower aims to ship ICs made on 130-nm process in 2005
- Sarnoff Introduces Silicon Proven ESD Design Tool Kit For ICs, Matched To Specific Foundry Processes
- Sarnoff ESDdoctor(TM) Offers ESD Solutions For New ICs, Trouble-Shoots Problems In Existing Chips
- Epson Licenses Sarnoff's TakeCharge ESD Design IP For High-Voltage Driver ICs Used In LCD Panels
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools