Jennic rolls out IP blocks for processors and frames in 10-Gbps networks

Jennic rolls out IP blocks for processors and frames in 10-Gbps networks
By Semiconductor Business News
April 12, 2002 (4:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020412S0132

SHEFFIELD, U.K. -- Jennic Ltd. here announced a range of intellectual-property (IP) blocks that can be used to create payload processors, framers and others for 10-gigabits-per-second (OC-192) networks.

The products from Jennic include an STS-192 SONET framer, a payload processor and an SPI-4.2 Interface. The IP blocks can be used separately, but are intended to be used with each other to develop complete ASSP devices.

"Our latest products offer customers the opportunity to accelerate their product development schedules and to realise products with major differentiating features over those of their competitors," said Jim Lindop, Jennic's CEO. "Jennic's silicon design services provide the capabilities required to achieve right first time silicon for devices of this speed and complexity."

The STS-192 SONET framer supports the standard SONET mappings down to 192 STS-1 channels and can be used as either a single STS-192 framer or as four indi vidual STS-48 framers.

The company's payload processor provides the capability to simultaneously encapsulate and decapsulate multiple channels of data using a variety of different protocols including Ten Gigabit, GFP, PPP and ATM.

The SPI-4.2 Interface allows the transfer of variable length packets and ATM cells between an OIF SPI-4.2 bus and a packet/cell processing engine such as the payload processor. The SPI-4.2 Interface supports up to 256 individual physical-layer channels and contains an integrated, channelised, FIFO. It supports a number of features that are required when used in channelised SONET applications.