IP Reuse Can Usher in a Renaissance
Electronic News
The 2003 International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies. The newest roadmap calls for widespread reuse of IP blocks greater than 1 million gates. These so called "very large blocks" are being implemented as templates, subsystems or platforms and not as a collection of individual cores. It would seem that IP reuse is now the key factor in design economics.
Using market forecasts for ASIC and ASSP design starts with process technology and the ITRS assumptions about increased IP block reuse, there will need to be 100 billion gates of re-used logic blocks in 2007's design starts. That would be 10 thousand blocks of million-gate size, re-used logic blocks.
Related Semiconductor IP
- Generative AI Edge Processor
- AXI NoC Non-Coherent Mesh
- CXS c/d/Lite Verification IP
- USB OTG 2.0 with xHCI Verification IP
- DDR5 RDIMM Verification IP
Related News
- Arasan acheives the Industry's First ASIL-D Certification for its CAN XL IP Core
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- VSIA ponders standards for software reuse
- Design And Reuse and Sci-worx are announcing a joint initiative on IP XML encapsulation technology and practice
Latest News
- ChipAgents Collaborates With NVIDIA to Launch Build-A-Chip-Bench for Autonomous Chip Design and Implementation
- Quintauris and Microchip Technology join forces to grow RISC-V® adoption
- BrainChip Launches Sequora: Edge AI That Doesn’t Just Recognize — It Understands and Responds
- GlobalFoundries selected to operate two new semiconductor fabs in New York under landmark U.S.-Japan initiative
- Siemens’ Tessent ecosystem enables direct test pattern execution via PCIe and USB