IP To Meet 2.5D Requirements
Steffora Mutschler, Semiconductor Engineering
May 8th, 2014
Widespread use of 2.5D is still at least a year out from becoming a viable option but specific technical requirements are being identified along the way.
The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon.
“The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASICs in a 2.5D structure is really not that different—same thickness of silicon; same processes; your bumps are smaller. But now you’re dealing with IPs that are different, made just for this.”
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- SoC test requirements debated <!-- verification -->
- DSP manufacturers to take hard look at 3G requirements
- ARC introduces 16/32-bit instruction set architecture to reduce memory requirements by up to 30 per cent
- UMC to Target SOC Designers' Requirements with New 1T-SRAM Memory Strategy
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools