INTERA Advances Neuromorphic Semiconductors for Next-Generation AI

A practical path to energy-efficient AI acceleration using standard semiconductor technology.

BARCELONA, Spain -- November 3, 2026 -- INTERA Group unveils its In-Memory Analog Computing (IMAC) technology, introducing an innovative semiconductor architecture designed to enable more energy-efficient and scalable artificial intelligence acceleration.

The rapid growth of artificial intelligence continues to drive unprecedented demand for computational power and energy efficiency.

In conventional computing systems, data must continuously move between memory and processors to perform calculations, creating the well-known von Neumann bottleneck.

This constant transfer of information increases energy consumption and processing latency while limiting scalability, presenting a fundamental challenge for the next generation of AI workloads.

In-Memory Analog Computing (IMAC) has emerged as a promising alternative by performing computations directly within memory-related circuitry. This approach significantly reduces data movement and enables the massive parallelism required by neural network workloads.

However, many existing in-memory computing solutions rely on emerging resistive memory technologies, such as Resistive Random-Access Memory (ReRAM) and memristors.

These technologies face several challenges, including device variability, conductance drift, limited endurance, and difficulties maintaining stable multilevel states at scale.

INTERA's IMAC Architecture: CMOS-Native Analog Computing

INTERA has developed a novel architecture designed to address these challenges through a fully CMOS-based active circuit element known as the Programmable Current Pulse Cell (PCPC).

Each PCPC generates a programmable current representing a synaptic weight, while the activation duration encodes the input signal.

The interaction between current amplitude and activation duration effectively performs the multiplication of the weight and input values.

The resulting electrical charge contributions are accumulated across a crossbar array, enabling highly parallel vector-matrix multiplication.

This architecture provides a foundation for energy-efficient neural network computation while reducing the need to transfer data repeatedly between memory and processing units.

Unlike approaches that depend on emerging resistive memory devices, INTERA's IMAC technology is designed to operate using standard CMOS semiconductor processes.

By leveraging established manufacturing technologies, the architecture aims to reduce implementation and production risks while supporting the development of scalable AI accelerators.

Key Advantages of INTERA's IMAC Technology

INTERA's CMOS-based In-Memory Analog Computing architecture offers four principal advantages for next-generation AI acceleration.

Standard CMOS Implementation

The PCPC architecture is designed to use established CMOS manufacturing processes, providing a practical foundation for semiconductor integration.

This approach reduces dependence on emerging memory technologies and may help simplify industrial adoption and manufacturing scalability.

Energy Efficiency and High Throughput

Computations are performed close to the data storage elements, reducing unnecessary data transfers between memory and processing resources.

The architecture also supports highly parallel operations, making it suitable for computationally demanding neural network workloads.

Reduced Technological Risk

By avoiding dependence on ReRAM-based computing elements, INTERA's approach addresses several technology-specific challenges associated with emerging non-volatile memory devices.

These include conductance variability, drift, and endurance limitations, although standard analog circuit design and calibration considerations remain relevant.

Scalable Architecture for AI Accelerators

The PCPC architecture provides a flexible foundation for developing AI accelerators that combine computational parallelism with reduced data movement.

Its design offers potential advantages in energy efficiency, latency, and computational density for future semiconductor implementations.

Target Applications

INTERA's IMAC technology is designed to serve as the foundation for a new generation of energy-efficient AI accelerators.

Potential application areas include:

• Data-Centre AI Processing: Supporting computationally demanding AI workloads through highly parallel processing architectures.
• Edge AI Devices: Enabling local inference in systems with strict power and latency requirements.
• Robotics: Supporting intelligent perception, decision-making, and embedded processing.
• Autonomous Systems: Providing efficient computing resources for responsive AI applications.
• Internet of Things (IoT): Enabling intelligent sensing and local data processing in connected devices.

These applications illustrate the potential of CMOS-based analog computing to support AI systems where computational performance, energy efficiency, and scalability are essential.

A Practical Path to Scalable AI Hardware

From both technological and commercial perspectives, INTERA's IMAC approach combines an innovative computing architecture with a pragmatic implementation strategy based on mature semiconductor manufacturing.

By integrating analog computation into standard CMOS technology, the architecture offers an alternative to in-memory computing approaches that rely on emerging resistive memory devices.

This strategy aims to facilitate the development of commercially viable AI accelerators while addressing key industry challenges related to energy consumption, data movement, and manufacturing complexity.

As demand for energy-efficient artificial intelligence continues to grow, INTERA's PCPC-based IMAC architecture offers a promising foundation for next-generation semiconductor solutions.

Through its work in advanced semiconductor IP, analog computing, and AI acceleration, INTERA continues developing technologies designed to support more efficient and scalable intelligent systems.

Discover INTERA's In-Memory Analog Computing Technology

Explore the technical foundations of INTERA's IMAC architecture and its potential for next-generation AI acceleration.

Explore the In-Memory Analog Computing Technology Brief

Meet INTERA at SEMICON Europa 2026

Interested in learning more about INTERA's CMOS-based analog computing architecture or exploring potential partnership opportunities?

Meet the INTERA team at SEMICON Europa 2026, taking place in Munich, Germany, from November 10 to 13.