Intel Unveils 10, 22nm Processes
Transistor-density metric proposed
Rick Merritt, EETimes
3/28/2017 08:45 PM EDT
SAN FRANCISCO – Intel will start making 10nm chips this year it claims will lead the industry in transistor density using a metric it challenged rivals to adopt. Separately, it announced a 22nm low-power FinFET node to compete for foundry business with fully depleted silicon-on-insulator (FD-SOI) from rivals such as Globalfoundries.
At 10nm, Intel will pack 100.8 million transistors per square millimeter. It estimated 10nm foundry processes now in production from TSMC and Samsung have about half that density.
Intel’s metric averages density of a small and a large logic cell. Specifically, it uses a two-input NAND cell with two active gates and a scan flip-flop cell with as many as 25 active gates.
To read the full article, click here
Related Semiconductor IP
- AP Memory VHM Controller
- High-performance, commercial-grade RISC-V CPU Core IP
- SWI3S Verification IP
- Secure Boot Loader
- Memory Subsystem
Related News
- Synopsys Delivers Certified EDA Flows and High-Quality IP for Intel 16 Process
- Siemens' Calibre platform now certified for IFS' Intel 16 process technology
- Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process
- Intel and Synopsys Expand Partnership to Enable Leading IP on Intel Advanced Process Nodes
Latest News
- proteanTecs Unveils Advanced Packaging Solutions to Improve Yield, Performance, and Reliability of Multi-Die Systems
- StarFive Launches Server-Class RISC-V IP to Accelerate Its Strategic Expansion into AI Computing Infrastructure
- Silvaco Announces Partnership with Dassault Systèmes to Advance First-Time-Right Semiconductor Manufacturing
- Socionext Broadens SoC Roadmap with Intel 18A-P Process Technology
- BrainChip and Neuromorphyx Announce an AKD1500 Embedded Developer Board, Bringing Neuromorphic AI to the Embedded Engineering Community