Freescale exec says central design pays dividends
Dylan McGrath
EE Times
(10/21/2005 7:58 PM EDT)
SAN FRANCISCO — Changes in Freescale Semiconductor Inc.'s approach to chip design, including standardizing on methodologies and appointing a renowned design manager, are contributing to improvements in the company's bottom line, according to Sumit Sadana, senior vice president of strategy and business development.
Sadana told EE Times Friday (Oct. 20) that, since joining Freescale in December 2004, he has implemented several changes to centralize design activity within the company in support of Freescale's overall goal of reducing cost structure and improving efficiency.
In addition, Sadana credited the addition of Chekib Akrout, the former IBM vice president who headed the design effort on the Cell processor, with adding experience, leadership and star power to Freescale's design efforts. Akrout quietly joined Freescale several months ago as vice president of design systems.
EE Times
(10/21/2005 7:58 PM EDT)
SAN FRANCISCO — Changes in Freescale Semiconductor Inc.'s approach to chip design, including standardizing on methodologies and appointing a renowned design manager, are contributing to improvements in the company's bottom line, according to Sumit Sadana, senior vice president of strategy and business development.
Sadana told EE Times Friday (Oct. 20) that, since joining Freescale in December 2004, he has implemented several changes to centralize design activity within the company in support of Freescale's overall goal of reducing cost structure and improving efficiency.
In addition, Sadana credited the addition of Chekib Akrout, the former IBM vice president who headed the design effort on the Cell processor, with adding experience, leadership and star power to Freescale's design efforts. Akrout quietly joined Freescale several months ago as vice president of design systems.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related News
- AMD names Motorola exec as its first VP of intellectual property
- Philips exec finds IP unusable, but necessary
- ARM exec slotted as next VSIA president
- BOPS Appoints Former ARM Exec., Carl Schlachte, as CEO
Latest News
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
- OpenAI and Broadcom unveil LLM-optimized inference chip
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification