Faraday Delivers System-Level ESD Protection Service to Reduce ASIC Time-to-Market
Hsinchu, Taiwan -- Mar. 17, 2020 -- Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today introduced its system-level ESD (electrostatic discharge) protection service. Faraday has successfully deployed this service in many ASIC projects, including factory automation applications, further shortening production lead times.
Leveraging its robust chip-package-PCB co-design capability, Faraday can provide customers with the system-level electrostatic design guidance of PCB layout to avoid potential system-level ESD design weakness; meanwhile, the essential analysis for system-level ESD-induced signal noise can be performed to determine the best design solution. In addition, Faraday’s reliability lab offers “one-stop system-level ESD test service” to meet customers’ system-level electrostatic related evaluation and test needs.
“Faraday not only provides common chip-level ESD protection service, but also offers the system-level service that further helps customers eliminate system-level electrostatic problems and achieve a smooth path to mass production,” said Jim Wang, vice president of operations at Faraday. “With our innovative ASIC expertise, we continue to work with our customers to provide the most efficient solutions to meet the growing demand for quality, enabling customers to seize market opportunities.”
About Faraday Technology Corporation
Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider, certificated to ISO 9001 and ISO 26262. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, LPDDR4/4X, DDR4/3, MIPI D-PHY, V-by-One, USB 3.1/2.0, 10/100 Ethernet, Giga Ethernet, SATA3/2, PCIe Gen4/3, and 28G programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan and China. For more information, visit www.faraday-tech.com
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- SMIC Offers a Full Set of ESD Protection Service to Enhance the Whole Chip ESD Design for Customers
- austriamicrosystems releases High-Voltage IO library offering 4KV ESD protection
- Sarnoff Europe Completes Management Buy-Out of Sarnoff's ESD Protection Business
- Sarnoff Europe Becomes Sofics, Announces New System-Level ESD Solutions for High-Voltage ICs
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers