Is design and reuse an impossible dream, ask panelists
Anne-Francoise Pele, EE Times
(12/03/2009 4:03 PM EST)
GRENOBLE — A panel session at the IP-ESC 2009 Conference this week in Grenoble, France, examined IP design and reuse from a business and technology perspective and urged IP and SoC providers to reach compromises.
With the global economic downturn, SoC designers became aware that by outsourcing critical IP they could decrease design time and improve time-to-market. However, collaboration between the IP vendor and the customer must be established, especially if IP reuse is to be achieved. In his introductory talk at the panel session, Jack Browne, senior vice president of sales and marketing at Sonics, said he sees a clear disconnection between the IP and SoC providers and called for a change to manage expectations on both sides.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
- Siemens to acquire Precision Innovations to expand AI-powered system-on-a-chip design exploration and optimization
- Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design
- Silvaco to Accelerate Physics-Based Digital Twins for Semiconductor Design and Manufacturing Using NVIDIA AI and Accelerated Computing
Latest News
- intoPIX to Demonstrate JPEG XS, IPMX and SMPTE ST 2110 Solutions at NAB Show New York 2026
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure