Arm Responds to RISC-V, and More
By Kevin Krewell, EETimes
October 11, 2019
Arm CEO Simon Segars announced the changes in his opening keynote at Arm TechCon. After decades of tight control over the Arm instruction set architecture (ISA), Arm has finally decided that it can allow its licensees to build their own custom instructions, which are often useful to accelerate specialized workloads.
To read the full article, click here
Related Semiconductor IP
- AP Memory VHM Controller
- High-performance, commercial-grade RISC-V CPU Core IP
- SWI3S Verification IP
- Secure Boot Loader
- Memory Subsystem
Related News
- When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform
- IAR platform boosts embedded development with upgraded toolchains for Arm and RISC-V
- Arm vs. RISC-V: Same DNA, Different Flight Paths
- AMI Announces a Shift-Left Initiative to De-Risk SoC Development for Arm Total Design in Collaboration with Arm and Synopsys
Latest News
- Silvaco Announces Partnership with Dassault Systèmes to Advance First-Time-Right Semiconductor Manufacturing
- Socionext Broadens SoC Roadmap with Intel 18A-P Process Technology
- BrainChip and Neuromorphyx Announce an AKD1500 Embedded Developer Board, Bringing Neuromorphic AI to the Embedded Engineering Community
- M31 Reports Nearly Fourfold Growth in Advanced-Node Royalties as Long-Term Investments Begin to Bear Fruit
- Andes Technology’s D23-SE RISC-V Processor Achieves ISO 26262 ASIL‑B and ASIL‑D Certification for Functional Safety Applications