Andes Technology has shut down Condor Computing
Condor flies no more
How an Austin start-up set out to push RISC-V into the data center but fell short.
By David Harold, John Peddie Reasearch
Andes Technology has shut down Condor Computing. Condor had been intended to push Andes into data-center-class RISC-V with an RVA23-based licensable core built around an unconventional time-based scheduling architecture. The IP now returns to Andes. The closure is a setback for Andes’ high-end ambitions and for RISC-V’s effort to establish credible alternatives to Arm and x86 in the data center.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
- 64-Bit 8-stage superscalar RISC-V processor
- Compact High-Speed 32-bit CPU for Real-time and Linux Applications
- Compact High-Speed 64-bit CPU for Real-time and Linux Applications
Related News
- Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
- Andes Technology Corp. Announces Its RISC-V CPU IP Serves as the Computing Engine in the New Renesas R9A02G020 MCU ASSP
- Andes Technology and TetraMem Collaborate to Build Groundbreaking AI Accelerator Chip with Analog In-Memory Computing
- Andes Announces First Customer Tape-Out Delivery of the AX46MPV for Cloud AI Acceleration
Latest News
- UMC Reports Sales for August 2026
- proteanTecs and MegaChips Collaborate to Bring Health and Performance Management Solutions to Next-Generation LSI Designs
- FortifyIQ Announces CAVP‑Validated ML‑DSA Verification Library for Post‑Quantum Secure Boot
- Baya Systems Chooses AdoreSys as Partner to Expand Semiconductor IP Availability Across China and Asia-Pacific
- GlobalFoundries and RAAAM Memory Technologies announce the joint development of next-generation GCRAM technology and test chip on FDX platform