Analog IPs Automate Integration, Tune to Fab Nodes

By Majeed Ahmad, EETimes (January 12, 2023)

System-on-chip (SoC) designs with heterogeneous voltage domains are increasingly moving away from custom analog IP to automated implementation so design engineers don’t have to worry about schedule slips caused by manual analog customizations. It also saves chip designers several months in the design process, while making analog circuits less susceptible to on-chip surroundings.

It’s important to note that automatically generated analog IP isn’t synonymous with off-the-shelf analog IP. Rather, analog IP generators bring the previously generated custom-design blocks into the design flow and employ specialized tools to tailor a suitable IP within hours. That, in turn, saves a lot of integration time and effort.

One of the key challenges that semiconductor engineers face when analyzing their solutions, however, revolves around how much analog designs can shrink when moving from one chip manufacturing process node to another. In other words, there are certain analog building blocks that don’t scale adequately to smaller IC manufacturing nodes. Moreover, while digital logic is getting cheaper in modern SoCs, not all analog functions can be incorporated economically.

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