Addressing AI While Keeping the MIPSiness In MIPS
By Sally Ward-Foxton, EETimes (July 5, 2024)
SANTA CLARA, Calif. — MIPS, now targeting AI applications for its application-specific data movement cores, is evolving with a careful eye on its strengths. “MIPS had a choice to make, because most of our RISC-V competitors are also publicly, or not publicly, pivoting hard towards AI,” MIPS CEO Sameer Wasson told EE Times. “The choice we made was to look at the problems others are not solving well and try to match them with what we can do better.”
For MIPS, this means data movement—something both deeply embedded in MIPS’ history and expertise, and absolutely critical to performant AI chips and systems.
“The problem we want to solve is to build the best data processing engine,” Wasson said. “It’s a mission which may not have the buzz to it [versus AI IP], relatively speaking, but I’m very comfortable with it, frankly, because it allows us to fly under the radar.”
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
Related News
- MIPS and INOVA Collaborate to put Physical AI into the palm of Robotic hands with new Reference Platform
- BrainChip Unveils Radar Reference Platform to Bridge the ‘Identification Gap’ in Edge AI
- MIPS I8500 Processor Orchestrates Data Movement for the AI Era
- Apple unleashes M5, the next big leap in AI performance for Apple silicon
Latest News
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification
- IBM Debuts World’s First Sub-1 Nanometer Chip Technology
- Panmnesia Unveils Next-Stage CXL Switch and Controller at ISCA 2026
- Akeana Collaborates with Samsung Electronics, fast-tracking RISC-V Customers, Ecosystem for Server and Agentic AI Silicon
- Arteris Technology Licensed by SiEngine for Next – Generation Automotive SoCs