A Multicore Platform for Energy and Throughput aware Applications

September 16, 2015 -- Researchers at Advanced Computer Architecture Laboratory (ACAL), HITEC University Taxila, Pakistan have developed a LEON3 based multicore reconfigurable processor platform for energy and throughput aware applications.

Recent advances in the field of computer architecture have marked power consumption as one of the major design constraints. Power optimization is now a prerequisite for not only portable and mobile computing systems but also for advanced multicore platforms. An energy efficient design strives to deliver optimum throughput while minimizing power consumption. Current research on energy efficient processor architectures targets various abstraction levels, spanning from integration technology to algorithmic optimizations.

The researchers have gained hands- on- experience on porting a processor on FPGA board running Linux, and some standard multicore benchmarks such as NAS Parallel Benchmarks. Subsequently, the basic single core processor was integrated with an cache line locking based adaptive cache memory, a run time reconfigurable Frequency Divider (DFS), and a performance monitoring unit. On successful porting of Linux OS and application benchmarks to test the reconfigurable cache memory system has extended to a multicore environment, with reconfigurable number of cores.

In order to build upon the concept of hardware realization of the previously runtime reconfiguration scheme, researchers at ACAL have created a hardware platform based on FPGAs on which the proposed multicore processor architecture has been mapped. This platform has a novel Fuzzy Logic based reconfiguration engine to optimize the system resources as per energy and throughput requirements of an application. It serves as a base for conducting research on several areas of multicore architectures such as the development of novel cache coherency protocols, memory management systems, cache replacement policies, hardware transactional memories, OS support for fine grained parallelism, Instruction Set Extension, Network on Chip, energy and throughput analysis, and hardware reconfiguration.

The reconfiguration engine of this system has been designed to measure the application throughput, energy consumption, and L1/L2 cache miss rate and based on the measured values, it turns-on/off the CPU cores, change their operating frequency (DFS-Dynamic Frequency Scaling), and resize cache memories. To measure the throughput of application hardware performance counters are used along with flag based ROI (region of interest) assertions.

This research helps in the development of an FPGA based reconfigurable multicore architecture that supports runtime reconfiguration of cache size and associativity, number of cores and operating frequency. By using the performance counters users can have a feedback of energy consumption, application throughput and cache miss rate. It also encourages the development of Fuzzy logic, Neural Nets, Game Programming or similar AI based algorithm to strike a balance between throughput and energy consumption of different workloads.

The platform is available as open source using GPLv2. This research was funded by National ICT R&D Fund, Pakistan. For further details please visit: http://emwi-tech.org/mppetap