A Big Week for RISC-V
By Sally Ward-Foxton, EETimes (February 10, 2022)
It’s been a banner week for the RISC-V ecosystem. The profile of the open-source instruction set architecture (ISA) has been raised by a pair of announcements. Let’s take a closer look.
Intel support
Earlier this week, Intel announced it would join RISC-V International as a premier member. Intel Foundry Services (IFS) will embrace designs built on multiple ISAs in order to compete with foundry giants Taiwan Semiconductor Manufacturing Co. and Samsung. Intel claims to be the only foundry offering IP optimized for x86, Arm and RISC-V.
The wording is crucial here, acknowledging as it does that RISC-V is joining x86 and Arm as a leading chip architecture.
Intel’s embrace of RISC-V means developing an ecosystem of its own. To that end, Intel is partnering with key RISC-V players, including CPU designer SiFive, AI accelerator chip company Esperanto, embedded CPU designer Andes Technology and data center CPU designer Ventana Microsystems. The partners will work with Intel to optimize their designs for Intel’s process technologies.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- The European Commission awards Frontgrade Gaisler funding under the Horizon Europe, Space R&I Work Programme: “COSMIC7” a development for RISC-V 7nm Microprocessor for Space Applications
- Tenstorrent releases RiescueD, a powerful framework for writing direct tests in RISC-V assembly
- Andes Technology Announces D23-SE: A Functional Safety RISC-V Core with DCLS and Split-Lock for ASIL-B/D Automotive Applications
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
Latest News
- Openchip unveils BER10: Europe’s new sovereign chip is here
- SEMIFIVE Accelerates Growth with 97% YoY Revenue Surge in H1 2026, Powered by ASIC Turnkey, Mass Production, and IP
- Andes Technology has shut down Condor Computing
- TIER IV joins JST’s Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving
- BrainChip Partners With Orama.AOI For AI-Fueled Defect Detection