SEGGER's emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements 2021-05-31 08:52:00 SoC Architecture & Assembly
Cadence Collaborates with TSMC to Accelerate Mobile, AI and Hyperscale Computing Application Development on N3 and N4 Processes 2021-05-31 08:48:00 EDA & Design Tools
Mirabilis Design and E-Elements Technology team up to provide concept-to-implementation design flow for AI applications 2021-05-27 17:05:00 EDA & Design Tools
Synopsys DesignWare PVT Subsystem Drives Performance, Power and Silicon Lifecycle Management on TSMC's N3 Process Technology 2021-05-27 15:09:00 IP Cores & Design
Silex Insight launches high performance (2Tbps) SM4-GCM Multi-booster 2021-05-27 13:51:00 IP Cores & Design
Precise-ITC launches 10G-1.6T Ethernet/FiberChannel/FlexO IP Core 2021-05-27 11:29:00 IP Cores & Design
AImotive launches aiWare4, featuring advanced wavefront processing, upgraded safety and low-power features 2021-05-27 11:22:00 IP Cores & Design
Cadence Unleashes Clarity 3D Solver on the Cloud for Straightforward, Secure and Scalable Electromagnetic Analysis of Complex Systems on AWS 2021-05-27 01:50:00 EDA & Design Tools
5G Ethernet Subsystem to reduce development time is now available 2021-05-26 16:09:00 IP Cores & Design
Imperas Simulation Reference Models selected by IAR Systems for Arm 64bit 2021-05-26 15:22:00 SoC Architecture & Assembly
Synopsys Digital and Custom Design Platforms Certified for TSMC's Latest 3nm Process Technology 2021-05-26 15:18:00 EDA & Design Tools
eYs3D Microelectronics, Co. Raises $7 Million Series A from Leading Industry Strategic Investors for Vision/AI Chips 2021-05-26 14:25:00 Strategic Partnerships
Hardent Joins Samsung SAFE IP Partner Program & Launches New Display IP Subsystem Solution in Collaboration with Rambus 2021-05-26 08:32:00 Misc