BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM
July 1, 2021 -- The Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure. Thanks to this support, users of RISC-V will be able to take advantage of vector computation capabilities of the RISC-V V-extension through C/C++ intrinsics.
Senior Research Engineer Roger Ferrer Ibáñez led the BSC contribution, which was financed by the European Processor Initiative (EPI). He commented: ‘The open-source instruction set architecture (ISA) RISC-V offers an unparalleled opportunity for Europe to regain technology leadership. Our work for EPI aims to help build the thriving ecosystem necessary for widespread adoption of RISC-V across a range of sectors, including high-performance computing and automotive applications. The RISC-V V-extension plays a crucial role in enabling this adoption.’
‘RVV has been extensively welcomed in the world of accelerated compute systems,’ added Andrew Richards, founder and CEO of Codeplay. ‘We are already building a SYCL based ecosystem on top of this architecture to provide high-performance computing and artificial intelligence developers with familiar tools and route to rapid integration.’
In addition to implementing the RISC-V V-extension application programming interface (API) intrinsics for C, BSC, Codeplay and SiFive have implemented the foundation of CodeGen for Vector Length Specific (VLS) and Vector Length Agnostic (VLA) autovectorization for RISC-V in LLVM.
The following assets are available via GitHub:
- Support for the v0.10 V-extension specification https://github.com/riscv/riscv-v-spec/releases/tag/v0.10
- Support for the RVV C intrinsics: github.com/riscv/rvv-intrinsic-doc/tree/v0.10
- Implementation of the draft vector calling convention: github.com/riscv/riscv-elf-psabi-doc/pull/171
An example of the RISC-V V-extension can be found here: github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_saxpy.c
This work complements other efforts within EPI to leverage vectors in widely used libraries; see, for example, the Fourier transform support in FFTW3, provided by Atos and SiPearl:
https://github.com/rdolbeau/fftw3/tree/riscv-v/simd-support
The European Processor Initiative has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement no. 826647
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