BrainChip Simplifies Deep Learning with Launch of MetaTF
2021-04-22 03:35:00
Misc
Semiconductor IP News Archive - Page 333 of 1964
sureCore Unveils New Low Voltage Register Files
2021-04-22 01:49:00
IP Cores & Design
Hardent Selected as Design Services Provider for New Xilinx Kria SOMs
2021-04-21 20:12:00
Strategic Partnerships
Codasip Announces FPGA Evaluation Platforms for RISC-V Processor Cores
2021-04-21 15:13:00
SoC Architecture & Assembly
Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications
2021-04-21 08:31:00
Strategic Partnerships
Synopsys Introduces PrimeLib Unified Library Characterization and Validation Solution for Accelerated Access to Advanced Process Nodes
2021-04-21 06:07:00
EDA & Design Tools
CAES Gaisler Signs Contract with the European Space Agency for New Advanced Space Processor
2021-04-21 05:24:00
Strategic Partnerships
Marvell Completes Acquisition of Inphi
2021-04-21 01:31:00
Strategic Partnerships
Pinnacle Imaging Systems Announces Denali 3.0 Soft ISP & HDR Sensor Module for New Xilinx Kria SOM Platform and Vision AI Starter Kit
2021-04-21 01:13:00
IP Cores & Design
Xilinx Introduces Kria Portfolio of Adaptive System-on-Modules for Accelerating Innovation and AI Applications at the Edge
2021-04-20 16:00:00
SoC Architecture & Assembly
Synopsys Unleashes PrimeSim Continuum Solution to Accelerate the Design of Hyper-Convergent ICs for Memory, AI, Automotive and 5G Applications
2021-04-20 15:14:00
EDA & Design Tools
Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs
2021-04-20 15:09:00
IP Cores & Design
Rambus Joins DARPA Toolbox Initiative with State-of-the-Art Security and Interface IP
2021-04-20 08:39:00
Strategic Partnerships
TSMC certifies Aprisa place-and-route solution from Siemens on TSMC's N6 process
2021-04-20 01:07:00
EDA & Design Tools
Expedera Introduces Its Origin Neural Engine IP With Unrivaled Energy-Efficiency and Performance
2021-04-19 15:00:00
IP Cores & Design
PLDA Introduces a Complete Line of PCIe IP for USB4, Enabling PCIe Support in USB4 Hubs, Hosts and Devices
2021-04-19 13:50:00
IP Cores & Design
DSP Concepts Enables Audio Weaver for the Cadence Tensilica HiFi 5 DSP
2021-04-19 11:37:00
SoC Architecture & Assembly
Logic Design Solutions Introduces the first NVMe HOST IP on POLARFIRE SoC FPGA
2021-04-19 07:48:00
IP Cores & Design
TSMC Boosts Capital Budget Again, to $30B
2021-04-19 06:41:00
Analysis & Insight
Cadence Pegasus Verification System Certified for Samsung Foundry 5nm and 7nm Process Technologies
2021-04-19 03:48:00
EDA & Design Tools