Need really big FPGAs? Xilinx will be taking the "3D" route for initial Virtex 7 parts
Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex 7 FPGAs using 28nm process technology. Every leading-edge process technology experiences a learning curve and initially, it’s hard to make the largest possible chips in any new process technology with commercially viable yields. So Xilinx faced a problem: it would not be able to make the largest possible Virtex 7 FPGAs for a while using 28nm technology. What to do for those leading-edge customers who always want to use the largest, fastest parts as soon as possible?
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