What Is Viral in CXL 3.0?
Introduction to CXL 3.0
CXL 3.0 is an open-standard interconnect technology that builds upon PCIe 6.0 to facilitate high-speed communication between CPUs and peripheral devices. With a doubled bandwidth of 64 GT/s and enhanced fabric capabilities, CXL 3.0 aims to optimize system-level flows, improve resource utilization, and enable new device types for composable disaggregated infrastructure.
Unveiling the Viral Feature
Viral is an error containment mechanism. CXL links and CXL devices are expected to be Viral-compliant. Viral support capability and control for enabling are reflected in the DVSEC. Viral is not a replacement for existing error-reporting mechanisms. Instead, its purpose is an additional error-containment mechanism.
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 / CXL 3.0 PHY & Controller
- CXL 3.0 Subsystem
- CXL 3.0 Dual Mode Controller
- CXL 3.0 Device Controller
- CXL 3.0 Host Controller
Related Blogs
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- What is cloud-based security lifecycle management for connected objects and why is it important?
- What is OTA in automotive? Over the air updates explained.
- CXL 3.0 Turns Up Scalability to 11
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins