CXL 3.0 Turns Up Scalability to 11
The CXL™ Consortium (of which Rambus is a member) has now released the 3.0 specification of the Compute Express Link™ (CXL) standard. CXL 3.0 introduces compelling new features that promise to increase data center performance, scalability and TCO. CXL has evolved rapidly from its introduction in 2019. The 1.0/1.1 specification enabled prototyping of CXL solutions. With 2.0 and the introduction of memory pooling, CXL reached the deployment phase. Now with CXL 3.0, we have capabilities that will power the scaling phase.
So, what’s new in CXL 3.0? Well, first up there’s a step function increase in data rate. CXL 1.x and 2.0 use the PCI Express® (PCIe®) 5.0 electricals for their physical layer: NRZ signaling at 32 Gigatransfers per second (GT/s). CXL 3.0 keeps that same philosophy of building on broadly adopted PCIe technology and extends it to the latest 6.0 version of the PCIe standard released earlier this year. That boosts CXL 3.0 data rates to 64 GT/s using PAM4 signaling.
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Related Semiconductor IP
- CXL 3.0 Controller
- PCIe 6.0 / CXL 3.0 PHY & Controller
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- CXL 3.0 Dual Mode Controller
- CXL 3.0 Device Controller
Related Blogs
- How CXL 3.0 Fuels Faster, More Efficient Data Center Performance
- Boosting Data Center Performance to the Next Level with PCIe 6.0 & CXL 3.0
- Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0
- What Is Viral in CXL 3.0?
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