What is the future for Network-on-Chip?

By EETimes

April 3, 2013

Sonics recently performed a survey about on-chip communications networks. This was conducted in a double blind manner so that they would not overly skew the results. They had 318 respondents and some interesting data showed up from the survey. Surprisingly, the survey showed that designers spend 28% of their time designing, modifying and verifying the networks on their chip. That seems like a very large amount of time especially since empirical data suggests that very little full chip verification is actually being performed, instead relying on the assumption that if all of the blocks are verified and the connectivity of the IP interconnect has been verified, then the system will operate correctly. While we all know this to be inherently false, most companies only seem to run a few system-level sanity tests.

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