Multi-format, multi-stream hardware Decoder for AV2
Next-generation, multi-format, multi-stream hardware Decoder
Overview
The Pulsar D400 Series Decoder IP is Allegro DVT’s next-generation, multi-format, multi-stream hardware Decoder, designed to deliver high-performance, silicon-efficient video decoding for advanced SoCs and ASICs.
Engineered for next-generation media workloads, the Pulsar D400 combines cutting-edge codec support with a scalable architecture, enabling semiconductor companies to integrate a robust, future-ready video decoding solution with confidence.
Broad Codec Support, Built for the Future
Built on a flexible multi-codec architecture, the Pulsar D400 Series supports all major video standards, including H.264, HEVC, VVC, VP9, JPEG and AV1, and introduces support for AV2, the next-generation open and royalty-free codec from the Alliance for Open Media (AOM).
As demand for higher efficiency and richer video experiences accelerates, AV2 represents a major evolution in compression technology. Building on AV1, it enables advanced use cases such as immersive video (AR/VR), multi-view streaming, enhanced screen content coding, and improved visual quality at lower bitrates.
With integrated AV2 support, the Pulsar D400 positions Allegro DVT at the forefront of open media innovation, offering a high-performance, real-time AV2 decoding solution designed for deployment-ready platforms.
Its scalable multi-core architecture supports real-time decoding up to 8K resolution, while optimizing:
- Silicon footprint
-
Memory bandwidth efficiency
- System-level integration
This ensures a balanced and production-ready solution, aligned with the requirements of next-generation streaming, broadcast, and data infrastructure.
Supported Formats
Video Codec Standards
-
AV2
-
AV1
- H.266 / VVC
-
H.265 / HEVC
-
H.264 / AVC
-
VP9
-
JPEG
Video Format Support
- Bit depth: 8-bit, 10-bit, 12-bit
- Chroma sampling: 4:2:0, 4:2:2, 4:4:4
Performance
- Real-time decoding up to 8K resolution
- Scalable architecture designed for evolving streaming workloads
- Multi-core scalability for flexible throughput
- Ultra-low latency decoding
Interface
- AMBA APB interface for control registers
- AMBA AXI interfaces for data access
Key features
- Ultra-low latency decoding (down to sub-frame)
- Scalable multi-core architecture for performance adaptation
- Source input compression
- Dynamic decoding parameter adjustment
- Smart decoding tools (ROI and advanced processing features)
- Video surveillance optimization features
- Color space conversion
- Bit depth conversion
- Chroma format conversion
- Multi-instance support
- Optimized memory bandwidth for system-level efficiency
Benefits
- Advanced AV2 support enabling future-proof video platform design
- Comprehensive multi-standard coverage across all major codecs
- High-performance, scalable architecture up to 8K resolution
- Optimized memory bandwidth and system efficiency
- Reduced silicon footprint for easier integration
- Low power consumption for energy-efficient designs
- Flexible and licensable IP tailored to SoC requirements
Applications
- AI servers & data centers
- Broadcast & professional video
- Mobile and Consumer devices
- Automotive platforms
- Surveillance systems
- AR/VR and immersive video
- Multi-view and interactive streaming
What’s Included?
- RTL source code
- C control software
- Bit-accurate reference model
- Comprehensive Documentation
Specifications
Identity
Compute
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Video Processing IP
What is Multi-format, multi-stream hardware Decoder for AV2?
Multi-format, multi-stream hardware Decoder for AV2 is a Video Processing IP core from Allegro DVT listed on Semi IP Hub.
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.