Verifying Processor Security, Part 2
This is the second post about Eli Singerman's keynote at the recent Jasper User Group. The first was Formally Verifying Processor Security. In the last couple of years, high-performance processors (not just Intel's) have been shown to be vulnerable to various side-channel attacks. These typically rely on using speculative execution to run code that should not be run, and then, despite the speculative execution being abandoned, some leak of data occurs. The first two such attacks were announced to the public at the start of last year with the names Spectre and Meltdown.
Eli is working on using formal approaches to prove that a future processor is immune to side-channel attacks, and also for analyzing the effects of mitigation on current processors (going back seven years). This is not just hardware that needs to be analyzed, but core firmware (in the processor itself) and other firmware (in devices like cameras and accelerators).
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Formally Verifying Processor Security
- Upcoming IoT Security Legislation: Vulnerability Disclosure - Part 2
- ST-Ericsson (Part 2): Diverse Offering
- Intel vs. ARM: In the Smartphone Era (Part 2)
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing