TSMC Unleashes Aggressive 28nm Strategy!
The most interesting presentation at the jam-packed TSMC Symposium last week for me was “Advanced Technology Updates" by Dr. BJ Woo. Coincidentally, I met with BJ during my last visit to Fab 12. Much of what we discussed was about TSMC being more aggressive this year but I wasn’t able to really connect the dots until her presentation. The example I will use here is 28nm but it certainly applies to all of the TSMC process nodes moving forward.
First let me tell you that BJ is engaging and a very credible semiconductor executive. She spent the majority of her 30 year career at Intel in Santa Clara designing both DRAM and microprocessors (she has 13 patents). In 2009 BJ joined TSMC taking responsibility for the advanced technology roadmap at 28nm and 20nm and today is Vice President of Business Development.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
- 10mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- 30mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- 40mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm
- 12-bit, 200 MSPS Pipeline ADC - TSMC 28nm
Related Blogs
- TSMC Gets 28nm Yield Up Over 80%
- TSMC 28nm Update Q3 2012!
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- ST-Ericsson (Part 3): Strategy And Outlook
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU