Connected by Arteris: Watching The Next Big Semiconductor Transition Unfold
Impressions from the 2nd Annual Chiplet Summit
From February 6th to 8th, 2024, a fascinating mix of engineers descended on the Santa Clara convention center for the Chiplet Summit. It felt like representatives from all aspects of the semiconductor ecosystem attended – providers of Semiconductor Intellectual Property (IP) like us, Electronic Design Automation (EDA) tool vendors, Wafer Fab Equipment (WFE) providers, Semiconductor Foundries, “Fabless” chip companies, and Integrated Design Manufacturers (IDMs) all in one place to discuss one thing – chiplets. The agenda varied from sessions discussing how to develop them, the architectures to integrate them, the substrates to assemble them on, the standards needed to connect them, the business models to enable them, and the industries and application domains setting requirements for them.
To read the full article, click here
Related Blogs
- The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
- Are IP subsystems the next big IP category?
- Ethernet in Cars - The Next Big Thing for Ethernet
- Is FPGA Intel Next Big Thing for IoT ?
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA