Microprocessor Report publishes extremely interesting comparison of STMicroelectronics SPEAr-1300 and Xilinx Zynq ARM-based, dual core application processors
Last month, STMicroelectronics introduced the latest in its line of SPEAr (Structured Processor Enhanced Architecture) application processors and Microprocessor Report has just published a very interesting article about the new products (paid subscription required). The SPEAr-1300 series is based on two 600MHz ARM Cortex-A9 microprocessor cores (upgraded from the 333MHz ARM9 cores used in the earlier SPEAr parts). Each ARM processor core in the SPEAr-1300 embedded application processor has two 32-kbyte L1 caches and the two processor cores share a 512-kbyte L2 cache. The SPEAr-1300 application processor also includes a number of hard-core IP peripherals including a Gigabit Ethernet port, a PCIe/SATA port, and two USB 2.0 ports. In addition, there are 1.3 million uncommitted ASIC gates that can be configured for specific applications and, in a throwback to the disco days of the 1980s, these ASIC gates are configured as a metal-defined gate array so the wafers can be stockpiled awaiting final metal designs.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Using Physical USB Devices with the Xilinx Zynq-7000 Virtual Platform
- PLD Overview: Xilinx and Altera
- Xilinx ARMs FPGAs, Altera to MIPSify Them
- Intel Eyeing Xilinx?
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing