Spec-based Coverage Closure with Synopsys VIP
Here, Synopsys R&D Director Bernie DeLay talks about achieving coverage closure for protocol compliance checking and integration testing by utilizing the built-in verification plans and functional coverage provided with VC VIP.
He describes configuration-aware coverage: how it correlates with the user’s specification
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Blogs
- Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
- Simplifying Multi-Domain Voltage-Control Verification with Synopsys AVSBus 2.0 VIP
- Webinar: Accelerating Verification Closure with PCIe Gen4 VIP
- Coverage Models - Filling in the Holes for Memory VIP
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins