Interlaken Synthesizable Transactor

The Interlaken Synthesizable Transactor is compliant with 1.2 specifications and verifies Interlaken interfaces. Interlaken is build on top of it to make it robust. Interlaken Synthesizable Transactor provides a smart way to verify the Interlaken component of a SOC or a ASIC in Emulator or FPGA platform. Interlaken Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

• Follows Interlaken specification as defined in Interlaken protocol definition v1.2
• Supports Interlaken look aside protocol specification v1.0
• Supports Interlaken retransmission extension specification 1.1
• Supports multi-channel implementation as per the specification
• Supports configurable number of serial lanes as per the specification
• Supports configurable burst max and burst short sizes
• Supports insertion of extra idle to guarantee the avoidance of burst short
• Supports scheduling calendar logic in the transmitter to choose the order in which the channels are serviced
• Supports optional scheduling enhancement to avoid unused bandwidth by using decision algorithm
• Each burst of transmitting data is encapsulated with burst control words before and after the data
• Supports configurable metaframe length
• Supports per channel inband and out of band flow control or both
• Supports Per-lane CRC-32 insertion into diagnostic words
• Supports Per lane skew insertion to test lane alignment
• Supports Configurable control to enable or disable the scrambler
• Supports 64B/67B encoding with inversion bits controllable
• Supports very flexible way to test sync and alignment for state machines at startup
• Supports test pattern generation and checking:
• Supports PRBS31
• Supports PRBS23
• Supports PRBS7
• Supports User defined pattern
• Supports Following error injection:
• Receive SerDes loses lock
• Receive logic loses word boundary sync
• Bad scrambler state
• Lane alignment failure
• Burst CRC24 Errors
• Flow Control Errors
• Unknown Control Word Types
• Bad 64B/67B Code words
• Diagnostic CRC32 Errors
• All types of CRC error injection
• Invalid coding for all control words
• Error injection in metaframes
• Short burst error injection
• Invalid burst boundary
• Test pattern error injection
• Comes with Interlaken Tx BFM, Interlaken Rx BFM
• Supports Interlaken interop recommendations 1.3 and 1.4
• Rich set of configuration parameters to control Interlaken functionality
• Supports 67 bit bus per lane or 1 bit serial lane to ease the debugging
• Supports 32, 20, 16, 10 and 8 bit serdes interface bus
• Supports On-the-fly protocol and data checking

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the Interlaken testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and functions used in verification env
• Documentation contains User's Guide and Release notes