New Synopsys Report Highlights Key Industry Insights on the Impact of Multi-Die Systems
For decades, Moore’s law enabled semiconductor companies to double the number of transistors in an integrated circuit (IC) every two years. As Moore’s law slows, device scaling for monolithic systems-on-chip (SoCs) is noticeably less while the cost of newer, more complex process nodes continues to steadily increase. However, the demand for faster, better, and smarter silicon is only growing as the exploding impact of “Smart Everything” and ubiquitous artificial intelligence (AI) drive a massive push for faster speeds and ever-more transistors. We call this intersection of Moore’s law scale complexity with new systemic complexity demands the SysMoore era.
Aart de Geus, Synopsys chair and chief executive officer, recently observed that semiconductor companies are revolutionizing both architectural function and form with new multi-die systems to help meet market demand. Indeed, disaggregating a large monolithic chip design into smaller, proven dies results in higher yields, lower silicon costs over time, and more customizable SKUs. de Geus, who penned the opening chapter of a new Synopsys industry insight report titled “How Quickly Will Multi-Die Systems Change Semiconductor Design?” notes that cross-industry collaboration has seen chip designers significantly increase connectivity density while reducing energy switching (per bit). The report also includes insights on multi-die systems from Ansys, Arm, Bosch, Google, Intel, and Samsung.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
- Industry Leaders Discuss "Overcoming the Challenges of Multi-die Systems Verification"
- A Primer on Multi-Die Systems
- Your New "Superpower": See Through "Hand-Off Walls" for Implementation PPA Insights on Early-Stage RTL
Latest Blogs
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP
- Why nonce reuse can break AES-GCM security in embedded systems
- PQSecure™-Agility Earns NIST CAVP Validation