Yawn... New EDA Leader Results Are Coming
We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.
Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce. I still have my brass-plated letter opener which Cadence gave to every employee in September 1990 when Cadence moved to the NYSE. Heck I even was excited to see the SVR (Silicon Valley Research, aka Silvar-Lisco) announcements. It was exciting to follow the industry then.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- ICCAD Keynote: Design of Secure Systems - Where are the EDA Tools?
- CES 2020: The robots are coming...
- Silicon IP has taken over CAE in EDAC results... showing how bad have been analyst in forecasting the IP market!
- Jim Hogan's top six SoC trends for 2012. Want to know what they are?
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions