Moore's Law: Wanted, Dead or Alive
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held on April 26 at the Computer History Museum in Mountain View, California. Iyer pointed out that process complexity has grown from node to node. Yes we already knew that—but in earlier node transitions the increased processing cost was offset by the doubled number of additional transistors per unit area you get for each jump. Iyer projected a graph showing that the reduced effective cost per transistor stops falling after the 32/28nm node. Here’s the graph:
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