Moore's Law and Semiconductor Design and Manufacturing
March 14, 2011
The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even a few atoms are out of place. So process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for, if we are to achieve low-power, high-performance, and high yield design goals.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related Blogs
- How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?
- Smart Manufacturing Makes Semiconductor Fabrication and Advanced Electronics Possible
- Introducing Fab.da: A Comprehensive, AI-Powered Solution for Efficient Semiconductor Manufacturing
- Pioneering Seamless Interoperability on Cloud Across the Semiconductor Design Ecosystem