Moore's Law and Semiconductor Design and Manufacturing
March 14, 2011
The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even a few atoms are out of place. So process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for, if we are to achieve low-power, high-performance, and high yield design goals.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Blogs
- How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?
- Reshoring Semiconductor Manufacturing
- Semiconductor Growth from AI-Driven Design Productivity
- Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?
Latest Blogs
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA
- Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments