Last VIP News of 2014
It’s likely that most of the current Semiwiki readers didn’t read this article posted in 2011, comparing Cadence and Synopsys with the Soviet Union and the USA, sharing the world in 1944 during the Yalta Conference. I was explaining in my post that Synopsys’s strong influence was on Design IP when Cadence’s preferred domain was on Verification IP. A kind of “Yalta effect” applied to the electronic design area (not to world regions!). If you missed this article, don’t worry as the content is no more relevant! Synopsys is still dominant in the IP business when excluding the large processor IP core segment (with $342 million revenues in 2013), but the company is also massively investing the VIP business, as we can see on the table below. To be fair, I must say that Cadence is also playing in Synopsys’s garden, investing in the Design IP business. But let’s take a look at the latest VIP news
To read the full article, click here
Related Semiconductor IP
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
Related Blogs
- Verification of UALink (UAL) and Ultra Ethernet (UEC) Protocols for Scalable HPC/AI Networks using Synopsys VIP
- Cowan's LRA model: Actual July 2010 global semicon sales $24.57bn; down 9.5 percent from last month (June)
- IP would be nothing without VIP...
- Intel Proves Last Year's Conventional Wisdom Wrong
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects