Is Low Power a Challenge? ICE-Grain Answers the Challenge

By SemiWiki

May 12, 2015

Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.

It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they are automatic, take them. But to get serious power saving you have to power down blocks, gate clocks, scale voltages and so forth. But this stuff is hard. The most advanced design groups have teams that specialize in this stuff but mainstream SoC groups find it challenging. It usually requires interaction between software and hardware and, unfortunately, the embedded software engineers do not really understand much about the chip, and the designers don't really understand the software peoples' issues. Often power saving registers are unused, at least in the first version of the design, since there isn't time to get it all working together. There is complex timing associated with powering blocks up and down or varying their frequency, and this is complex to manage in software since the software has other stuff it has to do in parallel. So the processor has to do more than run a device driver for as much as a millisecond or two while it all happens and that sort of programming is hard. Despite working in Semiconductor/EDA all my career, my PhD is in operating systems so I have the scars. I have written my share of device drivers.

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