Intel says fabless model collapsing... really?
There is an interesting discussion in the SemiWiki forum in response to the EETimes article: Intel exec says fabless model 'collapsing'. Definitely an interesting debate, one worth our time since the advertising click hungry industry pundits will certainly jump all over it. Clearly I’m biased since I helped build the semiconductor ecosystem. I will certainly try and be open minded here, but probably not.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Mark Bohr, a 33+ year Intel alum, and Brad Heaney, the Ivy Bridge program manager. This was clearly a scripted Intel PR piece, but also an opportunity for additional hyperbole and commentary.
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