How to reduce the risk when making the shift to RISC-V
In conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip
With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.
We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.
Vijay, what is the risk when making the shift to RISC-V?
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related Blogs
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- How to Design a RISC-V Space Microprocessor
- From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution