HiSilicon collaborates with Cadence on DDR4 PHY IP for TSMC 16FF
February 3, 2015
High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer to license the Cadence® Denali® DDR4 PHY IP, implemented on the TSMC 16nm FinFET process.
To read the full article, click here
Related Semiconductor IP
- DDR4 PHY
- TSMC CLN40LPP 40nm DDR4 PHY - 2933Mbps
- TSMC CLN28HPCPLVT 28nm DDR4 PHY - 2933Mbps
- TSMC CLN28HPCP 28nm DDR4 PHY - 2933Mbps
- TSMC CLN16FFPLLLVT 16nm DDR4 PHY - 4266Mbps
Related Blogs
- Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for Mobile, Cloud, and IoT Platforms
- See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+
- One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation
- Who needs DDR4 PHY running at 2667 Mbps?
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution