Next-Generation DDR4 and LPDDR4 IP in TSMC 16FF+ Enable 200Gb+ Data Transfers for Mobile, Cloud, and IoT Platforms
April 8, 2015
Consumer demand for entertainment and communication is changing the architecture of your electronic devices. And Cadence is providing key IPs necessary for SoC developers to quickly bring their products to market. Today Cadence is unveiling its first-silicon results for both DDR4 and LPDDR4 IP on TSMC's 16nm FinFET Plus (16FF+) process, with test chips operating at 3200Mbps. This speed can support the computation requirements for tomorrow’s high-resolution video and data bandwidth requirements of mobile, cloud, and networking devices. Figure 1 shows the fully integrated LPDDR4 package-on-package (POP) test chip and memory.
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