FPGAs as ASIC Alternatives: Past & Future

By EETimes

April 24, 2014

In my recent blog, 28nm – The Last Node of Moore's Law, I outlined the recent dramatic change that has occurred after many years of cost reduction associated with dimensional scaling. It is now clear that the 28nm technology note will provide the lowest cost-per-gate for years to come. In this blog we will assess the potential implications for the ASIC and the FPGA markets.

Over the last two decades, we have seen escalating mask set costs associated with dimensional scaling, along with accordingly escalating NRE costs. At the recent 2014 SEMI Industry Strategy Symposium (ISS), Ivo Bolsens, Xilinx CTO, presented the following chart illustrating ASIC design cost escalation:

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