The Increasingly Hazardous World of FPGA Verification
October 26, 2010
Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification issues as developers of non-programmable devices. This trend has been evident for quite a few years, but the number of FPGA users affected has grown from a tiny fraction to an entire upper tier of developers whose design size and complexity rival or even surpass many ASIC and SoC projects.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Blogs
- The interface makes the FPGA
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
- Will verification challenges overwhelm FPGA design?
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era