FPGA Chiplets Get a Power and Cost Makeover Thanks to New Partnership
QuickLogic and YorChip have formed a strategic partnership to develop Low-Power, Low-Cost UCIe FPGA Chiplets. These chiplets are optimized for low power consumption and low cost, opening new possibilities for a wide range of applications, including the fast-growing edge IoT and AI/ML markets.
What is UCIe?
UCIe (Unified Chiplet Interconnect Express) is an open standard for connecting small, modular blocks of silicon called chiplets. Monolithic chips, which are large and complex, are becoming increasingly difficult and expensive to design and manufacture. UCIe addresses this challenge by providing a standard way to connect chiplets. This makes it easier to design and manufacture chiplets and ensures that they can be easily interconnected with each other.
Why is this partnership important?
This partnership is important because it brings together two companies in the FPGA and chiplet industries. QuickLogic is a pioneer in the development of embedded FPGA (eFPGA) IP, and YorChip is a developer of UCIe-compatible IP. The combination of these two companies' expertise will create a powerful platform for the development of low-power, low-cost FPGA chiplets.
What are the benefits of FPGA chiplets?
FPGA chiplets offer a number of benefits over traditional FPGAs, including:
- Smaller size and lower power consumption
- Increased flexibility and modularity
- Faster time to market
- Lower development costs
What are the target markets for FPGA chiplets?
The target markets for FPGA chiplets include:
- Edge IoT
- AI/ML
- Automotive
- Defense
- Aerospace
- Industrial
- Medical
What is the future of FPGA chiplets?
The future of FPGA chiplets is bright. The growing demand for low-power, high-performance computing is driving the adoption of chiplets in a variety of applications. FPGA chiplets are well-positioned to capitalize on this growth, and the QuickLogic and YorChip partnership is a major step forward in the development of this technology.
Related Semiconductor IP
- UCIe IP Core
- UCIe 3.0 Verification IP
- Verification IP for UCIe
- UCIe Verification IP
- AXI to UCIe Bridge IP
Related Blogs
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring
- Power, Not Area: Why Edge GPU Design Is Entering a New Era
- 3 steps to shrinking your code size, your costs, and your power consumption
Latest Blogs
- The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
- From photon to actuation: How physical AI is redefining embedded compute
- Secure Boot for embedded Linux on Efinix Ti375C529: Getting started with KiviBoot-Linux
- Akida in High-Frequency Trading: The Smart Signal Layer
- Cadence Expands Sovereign AI in Europe: From Chips to AI Factories