Finfet's Struggles Boost Simpler, Cheaper FD-SOI
FD-SOI, seeking to grow its ecosystem, will get a boost from the remarks of KLA Tencor CEO, Rick Wallace, about the struggles his customers are having with finfets.
“In logic and foundry, with the introduction of the new 3-D gate architectures, the yield issues our customers are grappling with today are proving to be the most challenging that the industry have ever faced, and even the smallest variation and process margin can cause significant yield losses for these devices,’ says Wallace.
FD-SOI uses few masks and has less processing steps than finfet.
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