Fine-grained memory protection
In previous blog posts we have considered the damage, costs and underlying causes of memory unsafety. Having looked at conventional approaches to protecting processor systems we concluded that standard approaches such as MPUs, MMUs and privilege modes while having some value are limited in effectiveness.
We also noted that while languages like C/C++ give tremendous control to programmers there is also a lot of room for errors because of the use of pointers. Pointers are variables containing memory addresses.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- Are common memory protection mechanisms adequate?
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
- Anti-Fuse Memory With Gusto
- Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car