FD SOI Benefits Rise at 14nm
Consultant Handel Jones makes the case that companies should move rapidly to 14nm fully depleted silicon-on-insulator (FD SOI) to use the benefits this technology.
The semiconductor and electronics industries are adapting effectively to the increase in gate costs with scaling below 28nm. The following figure shows the latest projections for gate cost.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- FD-SOI at Samsung
- ARM 1176 in IBM SOI process demonstrates a cell-based flow
- Benefits Of Artisan Acquisition 'Coming Through', Says ARM CEO
- Jeff Bier's Impulse Response - The Rise of Licensable Cores
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car