Demystifying PCIe PIPE 5.1 SerDes Architecture
Artificial intelligence and machine learning are rapidly penetrating a wide spectrum of devices, driving the re-architecture of SoC designs and requiring more memory space and higher bandwidth to transfer and process data. This change requires higher speed interfaces and wider buses, paving the path for enhancements in the latest PCIe protocol specifications, as well as upgrades in PIPE (PHY Interface for the PCI Express) specification as the preferred PHY interface.
PIPE specification has evolved to version 5.1.1 not only to match the latest specifications but also to scale up for future enhancements in the protocols. SerDes architecture makes a PIPE 5 PHY protocol agnostic with all the protocol specific logic shifted to the controller. This simplifies the PHY design and allows it to be shared easily by different protocol stacks. SerDes architecture for PIPE interface achieves scalability by introducing several key changes to the responsibilities of the Physical Coding Sublayer (PCS) and Media Access Layer (MAC), along with updates to the signaling interface.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Power Management of PCIe PIPE Interface
- PCIe PIPE 4.4.1: Enabler for PCIe Gen4
- Demystifying PCIe Lane Margining Technology
- New PCIe TDISP Architecture Secures Device Interfaces with Virtual Servers
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions