PCIe PIPE 4.4.1: Enabler for PCIe Gen4

By Synopsys, Inc.

January 18, 2018

PCIe is a multi-layered serial bus protocol which implements dual-simplex link. It provides high speed data transfer and low latency owing to its dedicated point to point topology. To accelerate verification and device development time for PCIe based sub-systems, PIPE (PHY Interface for the PCI Express) architecture was defined by Intel. PIPE is a standard interface defined between PHY sub-layer (PCS – Physical Coding sub-layer) and MAC (Media Access Layer).

The first stable version of PIPE was published as PIPE 2.0 in 2007. Over the time, PIPE has evolved to support higher speeds and the added functionalities of next generation PCIe specifications. PIPE 4.4.1 specification, released in early 2017, is fully compliant with PCIe 4.0 base specification supporting 16GT/s speed. It has major improvements over PIPE 4.3, while maintaining backward compatibility. Following diagram illustrates PIPE interface, and the partitioning of PHY layer of PCIe.

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