DDR5 Is on Our Doorstep
October 15, 2018
The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the final standard is still expected before the end of the year.
At TSMC's OIP Ecosystem Forum, Cadence's Marc Greenberg and Micron's Ryan Baxter presented on DDR5 Challenges and Solutions. The two companies decided not to wait for the final ink to dry on the standard since engineering takes too long, so they agreed on a detailed spec that was close to what they expected the final standard to be.
To read the full article, click here
Related Semiconductor IP
- DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
- DDR5 MRDIMM PHY and Controller
- MRDIMM DDR5 & DDR5/4 PHY & Controller
- DDR5 Serial Presence Detect (SPD) Hub Interface
- DDR5 Controller - Ensures high-speed, efficient operation and compatibility of memory controllers
Related Blogs
- AMI for DDR5 Made Easy
- DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s
- How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard
- DDR5 - Off and Running
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP